1. Field of the Invention
The present invention relates to a signal transmission system in a bus-type network.
2. Description of the Prior Art
CSMA/CD has been proposed as a system for transmitting data via a bus-type network by use of a scrambling or prioritization circuit. With this system, the bus is monitored at all times so that a signal is transmitted promptly or after a predetermined period when no signal is detected on the bus. There is a possibility that data transmission is started simultaneously with data transmission from another terminal due to signal transmission delay--a phenomenon called collision hereinafter. To avoid this, the system is provided with means for detecting collision by comparing an output signal with a signal on the bus, so that data transmission is stopped when collision is detected. In this case, the bus may be designed to permit either one of the colliding data to pass through the circuit.
An example of this kind of bus is shown in FIG. 1 in which the bus is composed of wired OR circuits of open collectors. A, B and C are transmitting/receiving terminals.
FIG. 2 is a timing chart explaining the above-mentioned collision detection operation by the bus of FIG. 1. In this example, it is asumed that two terminals A and B start transmitting signals simultaneously at the point 0. After transmitting signals, the terminals A and B sample the signal on the bus. If the signal sampled by one of the terminals is different from that transmitted by that terminal, the terminal stops data transmission immediately. Referring to FIG. 2, collision is not detected by any terminals at the sampling points T.sub.1 and T.sub.2 where the signal on the bus is identical with the one transmitted by the two terminals A and B. At the point T.sub.3 where the signal on the bus is LOW though the terminal B outputs HIGH signal, the terminal B detects collision and stops data transmission immediately. The terminal A, which does not detect collision, continues data transmission. Thus, other data on the bus cannot be destroyed, because the terminal stops data transmission immediately after detecting collision.
Using the above system, it is possible to give higher priority to a particular packet. Since LOW signal is given higher priority than HIGH signal in this example, a particular packet is allowed to pass through the circuit prior to other packets if the particular packet has a series of LOW signals for the leading bits.
Collision detecting operation is conducted from the leading bit. If no collision is detected in the first frame, the detecting operation may be continued for the second and subsequent frames.
FIG. 3 shows a case where the two terminals A and B transmit first frames of the same data simultaneously. In this case, it is assumed that the two terminals A and B have different clock pulses. For simplicity, the bus is composed of wired OR circuits as described earlier. The receiving terminal C receives signals by the same clock pulse as the terminal B. After signal transmission, the terminals A and B sample signals on the bus at the center of each bit.
The terminals start data transmission simultaneously at the point T.sub.0. The difference in data output timing (T.sub.E1 .about.T.sub.E9) by the terminals grows larger with time because of the clock pulse error. However, collision will not be detected unless the data output timings of the terminals deviate with each other by more than a half bit before the final bit of a frame. Naturally, the terminal C having the same clock pulse as the terminal B can receive correct signals. Normally, in start-synchronized transmission, the clock is required to have such a high accuracy as to restrict a bit transmitting/receiving timing error to within 1/2 a bit for a frame. Since the example of FIG. 3 satisfies this requirement, the terminal C can receive transmitted data correctly.
FIG. 4 shows signal waveforms transmitted from the terminals A and B and that on the bus for the case where the terminals transmit frames of data sequentially. In this example, the starting bits of the terminals do not synchronize with each other because of difference in the clock pulse. At the point T.sub.c where the signal level is LOW on the bus while signal output from the terminal B is HIGH, the terminal B detects collision and stops data transmission immediately. As a result, the data transmitted from the terminal A survives and continues to be outputted onto the bus. Meanwhile, the terminal C, which receives signals by the start timing signal T.sub.s of the terminal B, is sampling data by the timing shown in FIG. 4. As result, signal output 0101 from the terminal A is possibly read as 0100. Namely, neither of the packets from the terminals A and B pass the circuit because data transmitted from the terminal A is destroyed by that from the terminal B.